This application claims the benefit of Korean patent application No. 2000-72245, filed on Dec. 1, 2000 in Korea, which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to an array substrate having thin film transistors (TFTs) each implanting a compact structure.
2. Discussion of the Related Art
In general, liquid crystal display (LCD) devices make use of optical anisotropy and polarization properties of liquid crystal molecules to control arrangement orientation. The arrangement direction of the liquid crystal molecules can be controlled by an applied electric field. Accordingly, when an electric field is applied to liquid crystal molecules, the arrangement of the liquid crystal molecules changes. Since refraction of incident light is determined by the arrangement of the liquid crystal molecules, display of image data can be controlled by changing the electric field applied to the liquid crystal molecules.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
The typical liquid crystal display (LCD) panel has an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, usually includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs), and pixel electrodes.
FIG. 1 is an exploded perspective view illustrating a typical LCD device. An LCD device 11 includes an upper substrate 5 and a lower substrate 22 that are opposed to each other, and a liquid crystal layer 14 interposed therebetween. The upper substrate 5 and the lower substrate 22 are called a color filter substrate and an array substrate, respectively. On the upper substrate 5, a black matrix 6 and a color filter layer 7 including a plurality of red (R), green (G), and blue (B) color filters are formed. The black matrix 6 surrounds each color filter such that an array matrix feature is formed. Further on the upper substrate 5, a common electrode 18 is formed to cover the color filter layer 7 and the black matrix 6.
On the lower substrate 22 on a side opposing the upper substrate 5, thin film transistors (TFTs) xe2x80x9cTxe2x80x9d are formed in shape of an array matrix corresponding to the color filter layer 7. In addition, a plurality of crossing gate and data lines 13 and 15 are positioned such that each TFT xe2x80x9cTxe2x80x9d is located near each crossing portion of the gate and data lines 13 and 15. The crossing gate and data lines define a pixel region xe2x80x9cPxe2x80x9d. A pixel electrode 17 is formed on the pixel region xe2x80x9cPxe2x80x9d. The pixel electrode 17 is made of transparent conductive material, such as ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide), which has excellent light transmissivity.
In the above-mentioned LCD panel, the liquid crystal molecules of the liquid crystal layer 14 are arranged in accordance with the signals applied to the pixel electrode 17 through the TFT xe2x80x9cTxe2x80x9d. The light passing through the liquid crystal layer 14 is controlled by the arrangement of the liquid crystal molecules.
FIG. 2 is a partial plan view of a conventional array substrate of active matrix liquid crystal display (AM-LCD). As shown in FIG. 2, the array substrate 22 of an AM-LCD includes a thin film transistor xe2x80x9cTxe2x80x9d, a pixel electrode 17 and a storage capacitor xe2x80x9cCxe2x80x9d. A gate line 13 is arranged in a transverse direction and a data line is arranged perpendicular to the gate line 13 in the array substrate 22. A pair of gate line 13 and data line 15 define a pixel region xe2x80x9cPxe2x80x9d. The TFT xe2x80x9cTxe2x80x9d includes a gate electrode 26, a source electrode 28, a drain electrode 30 and an active layer 24, and is arranged at one corner of the pixel region xe2x80x9cPxe2x80x9d where the data line 15 crosses the gate line 13. The gate electrode 26 extends longitudinally from the gate line 13 into the pixel region xe2x80x9cPxe2x80x9d and the source electrode 28 extends transversely from the data line 15 into the pixel region xe2x80x9cPxe2x80x9d. The drain electrode 30 is spaced apart from the source electrode 28 to form a channel region on the active layer 24. The storage capacitor xe2x80x9cCxe2x80x9d is a storage-on-gate type capacitor in which a portion of the pixel electrode 17 overlaps a portion of the gate line 13. The portion of the gate line 13 serves as a first capacitor electrode and the portion of the pixel electrode 17 serves as a second capacitor electrode. Although not shown in FIG. 2, an insulator serving as a dielectric layer in the storage capacitor is interposed between the gate line 13 and the pixel electrode 17, thereby forming an MIM (metal-insulator-metal) structure.
The operation of the TFT xe2x80x9cTxe2x80x9d and the capacitance of the storage capacitor xe2x80x9cCxe2x80x9d have an influence on the operating characteristics of the array substrate shown in FIG. 2. Therefore, it is very important that the structure and configuration of the TFT and storage capacitor should be designed and fabricated properly.
The thin film transistor (TFT) xe2x80x9cTxe2x80x9d generally has the channel region on the active layer 24 between the source and drain electrodes 28 and 30. Thus, the operating characteristics of the TFT are dependent on the channel region""s configuration, such as a channel width xe2x80x9cWxe2x80x9d and a channel length xe2x80x9cLxe2x80x9d. Furthermore, a portion of the drain electrode 30 overlaps a portion of the gate electrode 28, thereby forming an overlapped area xe2x80x9cMxe2x80x9d. Due to this overlapped area xe2x80x9cMxe2x80x9d, a gate-drain parasitic capacitance Cgd occurs in the TFT xe2x80x9cTxe2x80x9d. Since this parasitic capacitance Cgd has a bad influence on the operating characteristics of the TFT, decreasing the parasitic capacitance Cgd is a significant issue when designing the thin film transistor. In the thin film transistor, the parasitic capacitance can be given by following equation (1),                               C          gd                =                  ϵ          ⁢                      xe2x80x83                    ⁢                                    A              gd                                      d              gd                                                          (        1        )            
where Agd denotes the overlapped area xe2x80x9cMxe2x80x9d, dgd denotes a distance between the gate electrode 26 and the drain electrode 30, and epsilon ∈ is the permittivity of the dielectric layer. From the above equation, it is easily noticeable that the parasitic capacitance Cgd decreases as the overlapped area xe2x80x9cMxe2x80x9d becomes smaller.
Furthermore, the parasitic capacitance Cgd deteriorates the liquid crystal layer and is closely related to a direct current offset voltage xcex94Vp. The relation between Cgd and xcex94Vp is expressed by the following equation (2),                               Δ          ⁢                      xe2x80x83                    ⁢                      V            P                          =                                            V              SC                        -                          V              PC                                =                                    V              g                        ⁢                          xe2x80x83                        ⁢                                          C                gd                                            C                t                                                                        (        2        )            
where voltage Vsc denotes a center voltage of a signal voltage, voltage Vpc denotes a center voltage of the pixel electrode, voltage Vg denotes voltage of the gate electrode, and the total capacity Ct=Cgs+CS (storage capacitor)+CLc (liquid crystal capacitor). If Cgd is much smaller than CS or CLC in the equation (2), the denominator Ct equals Cs+CLC, and will thus be assumed a constant. Accordingly, the magnitude of xcex94Vp is proportional to the size of Cgd. As the Cgd becomes smaller, the operation characteristics of the array substrate improve.
The direct current offset voltage xcex94Vp contributes to inferior display images by causing afterimages, image inconsistency and poor reliability of the LCD. Thus, to obtain superior video quality, the size of xcex94Vp should be reduced. According to the equation (2), to lower the xcex94Vp value, the Cgd must also be lowered, which can be accomplished by decreasing the overlapped area xe2x80x9cMxe2x80x9d. Further, if the Cgd is fixed at a certain value, the xcex94Vp value is compensated by the common voltage.
However, the size of the overlapped area xe2x80x9cMxe2x80x9d varies because the gate and drain electrodes 26 and 30 can be misaligned during the manufacturing processes, thereby causing the variation of the Cgd value. Therefore, the xcex94Vp value also changes, and thus it is very difficult to compensate the xcex94Vp value using the common voltage.
Accordingly, the thin film transistor having the above-mentioned structure and configuration shown in FIG. 2 has the following problems. First, if the misalignment occurs between the gate electrode 26 and the drain electrode 30, the size of the overlapped area xe2x80x9cMxe2x80x9d varies. Second, since the thin film transistor xe2x80x9cTxe2x80x9d is positioned at one corner of the pixel region xe2x80x9cPxe2x80x9d, the aperture ratio of the pixel decreases, thereby deteriorating the brightness of the liquid crystal panel. To overcome these problems, another TFT structure and configuration are introduced as shown in FIG. 3.
FIG. 3 is a partial plan view of another conventional array substrate of active matrix liquid crystal display (AM-LCD). As shown in FIG. 3, the thin film transistor (TFT) xe2x80x9cTxe2x80x9d is positioned over the gate line 13 compared the TFT shown in FIG. 2. Since the TFT is not positioned at one corner of the pixel region xe2x80x9cPxe2x80x9d, the aperture ratio increases and the brightness of the liquid crystal panel is also raised. Further in FIG. 3, since the channel region xe2x80x9cCHxe2x80x9d on the active layer 24 has an L shape between the source and drain electrodes 28 and 30, the operating characteristics of the TFT xe2x80x9cTxe2x80x9d improve.
However, since a portion of the gate line 13 serves as a gate electrode and the TFT xe2x80x9cTxe2x80x9d is formed on this portion of the gate line 13, there are other problems occurring in the storage capacitor xe2x80x9cCxe2x80x9d. Namely, the size and capacitance of the storage capacitor xe2x80x9cCxe2x80x9d are lessened because the TFT xe2x80x9cTxe2x80x9d occupies much space on the gate line 13. Therefore, it is rather difficult to obtain an enough capacitance of the storage capacitor xe2x80x9cCxe2x80x9d. Further, if the misalignment occurs between the gate electrode (a portion of the gate line 13) and the drain electrode 30, the overlapped area xe2x80x9cMxe2x80x9d changes. Thus, the afterimage or the image inconsistency may occur in the LCD device.
FIG. 4 is a partial plan view of another exemplary of the conventional array substrate for use in an active matrix liquid crystal display (AM-LCD). In FIG. 4, a gate electrode 26 extends from the gate line 13 into the pixel region xe2x80x9cPxe2x80x9d, and the source electrode 28 extends from the data electrode 15 over the gate line 13. The gate electrode 26 has an L shape, and the drain electrode 30 is shaped like L. A first portion of the drain electrode 30 overlaps a portion of the gate electrode 26 and a second portion of the drain electrode 30 contacts the pixel electrode 17 through a contact hole 32. The TFT xe2x80x9cTxe2x80x9d is positioned both over the gate line 13 and at one corner of the pixel region xe2x80x9cPxe2x80x9d, and thus, the TFT xe2x80x9cTxe2x80x9d occupies less space of the gate line 13. Therefore, the size of the storage capacitor xe2x80x9cCxe2x80x9d can increase and the capacitance thereof can also increase. Further, the aperture ratio is rather improved than the array substrate shown in FIG. 2.
Further in FIG. 4, the channel region xe2x80x9cCHxe2x80x9d on the active layer 24 between the source and drain electrodes 28 and 30 has an L shape like the TFT shown in FIG. 3, the channel width xe2x80x9cWxe2x80x9d is enlarged and the operating characteristics of the TFT xe2x80x9cTxe2x80x9d also improve. However, since the misalignment may occur between the gate electrode 26 and the drain electrode 30, the overlapped area xe2x80x9cMxe2x80x9d changes like the TFT shown in FIG. 3. Thus, afterimage or image inconsistency may occur in the LCD device because of the variation of the gate-drain parasitic capacitance Cgd.
Accordingly, the present invention is directed to an array substrate for use in an LCD device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide an array substrate having an increased aperture ratio and a storage capacitor having sufficient capacitance.
Another advantage of the present invention is to provide an array substrate having improved operating characteristics and narrow variation in a gate-drain parasitic capacitance Cgd.
Another advantage of the present invention is to provide a method of manufacturing an array substrate having improved operating characteristics and narrow variation in a gate-drain parasitic capacitance Cgd.
Additional features and advantages of the invention will be set forth in the description that follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an array substrate for use in a liquid crystal display device includes a substrate; a gate line arranged in a transverse direction on the substrate; a data line arranged perpendicular to the gate line and forming a pixel region with the gate line; a thin film transistor positioned near an intersection of the gate and data lines; and wherein the thin film transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode; wherein the gate electrode has a slanted corner slanted to the gate line; wherein the source electrode has a U shape and is positioned over the gate electrode; wherein the drain electrode has a drain protrusion which is positioned over the gate electrode and slanted corner and located inside the U-shaped source electrode; wherein the drain protrusion is spaced apart from the U-shaped source electrode so as to form a channel region therebetween; and wherein an imaginary axis of the U-shaped source electrode and drain protrusion forms an angle with the gate line; a pixel electrode contacting the drain electrode.
In the above-mentioned array substrate, the angle between the imaginary axis and the gate line ranges from 30 to 60 degrees. In one aspect, the angle is 45 degrees. Beneficially, the U-shaped source electrode and the drain protrusion can be positioned over the gate line.
The array substrate further comprises a longitudinal pattern that is formed of the same material as the active layer and connected with the active layer. The longitudinal pattern has the same shape as the data line and is positioned below the data line.
In the above array substrate, the pixel electrode is made of a transparent conductive material selected from a group consisting of indium tin oxide and indium zinc oxide. Further, the above array substrate further comprises a gate insulation layer between the gate electrode and the active layer, and a storage capacitor which includes a portion of the gate line as a first capacitor electrode, a second capacitor electrode and the gate insulation layer as a dielectric layer. Here, the gate insulation layer is an inorganic material selected from a group consisting of silicon nitride and silicon oxide.
In another aspect, a method of fabricating an array substrate for use in a liquid crystal display device includes the steps of: forming a gate line and a gate electrode on a substrate, the gate line arranged in a transverse direction, and the gate electrode extended from the gate line; forming a data line perpendicular to the gate line, thereby defining a pixel region with the gate line; forming an active layer over the gate electrode; forming a source electrode and a drain electrode when forming the data line; and wherein the source electrode has a U shape and is positioned over the gate electrode; wherein the drain electrode has a drain protrusion which is positioned over the gate electrode and inside the U-shaped source electrode; wherein the drain protrusion is spaced apart from the U-shaped source electrode so as to form a channel region therebetween; and wherein an imaginary axis of the U-shaped source electrode and drain protrusion forms an angle with the gate line; forming a pixel electrode contacting the drain electrode.
In the above-mentioned method, the gate electrode has a slanted corner slanted to the gate line, and the drain protrusion overlaps the slanted corner of the gate electrode. The angle between the imaginary axis and the gate line ranges from 30 to 60 degrees. In one aspect, the angle is 45 degrees. Beneficially, the U-shaped source electrode and the drain protrusion can be positioned over the gate line.
The above method further comprises a step of forming a longitudinal pattern, which is formed of the same material as the active layer and connected with the active layer, when forming the active layer. The longitudinal pattern has the same shape as the data line and is positioned below the data line.
In the above method, the pixel electrode is made of a transparent conductive material selected from a group consisting of indium tin oxide and indium zinc oxide. Further, the above method further comprises a step of forming a gate insulation layer between the gate electrode and the active layer, and a step of forming a second capacitor electrode on the gate insulation layer and over the gate line when forming the data line, thereby forming a storage capacitor. The storage capacitor includes a portion of the gate line as a first capacitor electrode, the second capacitor electrode and the gate insulation layer as a dielectric layer. Here, the gate insulation layer, as a dielectric layer, is an inorganic material selected from a group consisting of silicon nitride and silicon oxide.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.